FPGA notes

CI

Most recent prior art: Poly94 GitLab CI (related: Tracking FPGA design build metrics with low infrastructure footprint)

Register map generators

• Cheby: https://gitlab.cern.ch/be-cem-edl/common/cheby
• peakrdl?

Simulation (and other forms of testing/validation)

• Verilator
• VUnit (Python)
  • really nice interface, but performance?
• SVUnit
• iverilog: https://github.com/blazer82/gb.fpga
• https://news.ycombinator.com/item?id=23760319 Chisel advocate

Q: When to use Verilator vs iverilog vs cocotb? (in Poly94 we use all of them in some way)

Verilator

Q: How to build with debugging symbols? A: You can pass --runtime-debug when invoking Verilator. However, it seems to have dramatic impact on compilation time (depending on the design, of course). If it’s too much and GCC gets stuck for minutes, consider passing just -CFLAGS -ggdb -LDFLAGS -ggdb.

Q: How to create a library instead of an executable? (See this SO question: https://stackoverflow.com/q/78452431)

Q: How to generate a trace (VCD)? A:

1. --trace
2. Verilated::traceEverOn(true);
3. must implement double sc_time_stamp()

Verilog

Code style: https://mcejp.gitlab.io/Poly94/code-style.html

VCD tooling

• C++ parser: https://github.com/ben-marshall/verilog-vcd-parser
• CLI viewer: https://github.com/yne/vcd
• Python package: https://pypi.org/project/Verilog_VCD/ (unmaintained since 2016)
  • Github mirror: https://github.com/zylin/Verilog_VCD

Q: How to render SVG from VCD? A: One approach is vcd2json + WaveDromPy